Preview

Digital Transformation

Advanced search

Analysis and Synthesis March Memory Tests

Abstract

The paper shows the relevance of testing storage devices in modern computing systems. Mathematical models of memory device faults and the efficiency of their detection, in particular, complex pattern sensitive faults of the PNPSFk type, based on classical march memory tests are presented. Limit estimates are given for the completeness of coverage of such faults depending on the number of memory cells involved in the fault. The necessity of synthesis of memory march tests characterized by high efficiency of PNPSFk failure detection is substantiated. The concept of a primitive providing conditions for activation and detection of various types of PNPSFk is defined. Examples of analysis and synthesis of memory march tests with different coverage of PNPSFk faults are given. The March OP memory test is synthesized, which is characterized by the maximum completeness of PNPSFk fault coverage and has the lowest time complexity compared to the known memory march tests, which provide the same comprehensiveness of coverage of complex memory device faults.

About the Authors

V. N. Yarmolik
Belarusian State University of Informatics and Radioelectronics
Belarus

Doctor of Science (Technical), Professor, Professor of Information Technology Software Department

6 P. Brovka St., 220013 Minsk



V. A. Levantsevich
Belarusian State University of Informatics and Radioelectronics
Belarus

Master of Science (Technology), Senior Lecturer of the Information Technology

6 P. Brovka St., 220013 Minsk



D. V. Demenkovets
Belarusian State University of Informatics and Radioelectronics
Belarus

Master of Science (Technology), Senior Lecturer of the Information Technology

6 P. Brovka St., 220013 Minsk



References

1. M. L. Bushnell, V. D. Agrawal. Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits. New York: Kluwer Academic Publishers, 2000. 690 p.

2. L. T. Wang, C. W. Wu, X. Wen. VLSI Test Principles and Architectures: Design for Testability. Amsterdam: Elsevier, 2006. 808 p.

3. V. N. Yarmolik. Kontrol i diagnostika vychislitelnykh system [Control and diagnostics of computing systems]. Minsk: Bestprint, 2019. 387 p. (in Russian).

4. The International Technology Roadmap for Semiconductors: 2003 Edition (ITRS’2003). San Jose: Semiconductor Industry Association, 2003. 65 p.

5. A. K. Sharma. Advanced Semiconductor Memories: Architectures, Designs, and Applications. London: John Wiley & Sons, 2003. 652 р.

6. A. J. Goor. Testing Semiconductor Memories: Theory and Practice. Chichester: John Wiley & Sons, 1991.

7. V. N. Yarmolik. Nerazrushayushcheye testirovaniye zapominayushchikh ustroystv [Nondestructive testing of storage devices]. Minsk: Bestprint, 2005. 230 p. (in Russian).

8. S. V. Yarmolik, A. P. Zankovich, A. A. Ivanyuk. Marshevyye testy dlya samotestirovaniya OZU [Marching tests for self- testing of RAM]. Minsk: Bestprint, 2009. 270 p. (in Russian).

9. M. Marinescu. Simple and Efficient Algorithms for Functional RAM Testing: IEEE Int. Test Conf. IEEE Computer Society Press, 1982. pp. 236–239.

10. C. Nair, S. Thatte, J. Abraham. Efficient Algorithms for Testing Semiconductor Random-Access Memories: IEEE Int. Test Conf. IEEE Transactions on Computers, 1978. vol. 27, no. 6, pp. 572-576.

11. D. S. Suk, S. M. Reddy. A March Test for Functional Faults in Semiconductor Random-Access Memories: IEEE Trans. on Computers. IEEE Transactions on Computers, 1981. vol. 30, no. 12, pp. 982–985.

12. A. J. Goor, G. N. Gaydadjiev, V. N. Yarmolik, V. G. Mikitijuk. March LR: A test for Realistic Linked Faults: 14th VLSI Test Symposium. IEEE Computer Society Press, 1996. pp. 272–280.

13. A. J. Goor, G. N. Gaydadjiev, V. N. Yarmolik, V. G. Mikitjuk. March LA: A test for Linked Memory Faults: Proc. of the 1997 European Design and Test Conference (ED&TC’97). IEEE Computer Society Press, 1997. 627 p.

14. K. L. Cheng, M. F. Tsai, C. W. Wu. Efficient neighborhood pattern-sensitive fault test algorithms for semiconductor memories: 19th VLSI Test Symposium. IEEE Computer Society Press, 2001. pp. 225–237.

15. P. Cascaval, S. Bennett. Efficient March test for 3-coupling faults in random access memories. Microprocessors and Microsystems, Elsevier, 2001. vol. 24, no. 10, pp. 501–509.

16. D. C. Kang, S. B. Cho. An efficient built-in self-test algorithm for neighborhood pattern sensitive faults in high-density memories: Proc. 4th Korea-Russia Int. Symposium on Science and Technology. IEEE Service Center, 2000. vol. 2, pp. 218–223.

17. K. L. Cheng, M. F. Tsai, C.W. Wu. Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories. IEEE Transactions on Computer, IEEE Press, 2002. vol. 21, no. 11, pp. 1328–1336.

18. B. F. Cockburn. Deterministic tests for detecting single V-coupling faults in RAMs. Journal of Electronic Testing: Theory Applicat, Springer, 1994. vol. 5, no. 1. pp. 91–113.

19. V. N. Yarmolik, I. Mrozek, S. V. Yarmolik. Psevdoischerpyvayushcheye testirovaniye zapominayushchikh ustroystv na baze marshevykh testov tipa March A [Pseudo-exhaustive memory testing based on March A]. Informatika. Minsk, 2020. № 2 (17). pp. 54–70. (in Russian).

20. V. N. Yarmolik, Y. Klimets, S. Demidenko. March ps(23n) test for DRAM pattern-sensitive faults: Proc. of the 7th AsianTest Symposium. IEEE Computer Society, 1998. pp. 354–357.


Review

For citations:


Yarmolik V.N., Levantsevich V.A., Demenkovets D.V. Analysis and Synthesis March Memory Tests. Digital Transformation. 2021;(2):45-55. (In Russ.)

Views: 2587


Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.


ISSN 2522-9613 (Print)
ISSN 2524-2822 (Online)